1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a wiring configuration used for permitting high-speed access to a signal line for selecting a memory cell in a memory in which cell selection is made by use of the hierarchical structure such as a duplex word line system.
2. Description of the Related Art
As the integration density is increased and the operation speed of semiconductor devices such as ICs and LSIs is enhanced, a problem of time delay caused by the wirings thereof becomes serious. The delay time (which is hereinafter referred to as wiring delay time) caused by the wiring in the semiconductor device is determined by the product R.multidot.C of the total sum C of load capacitances (such as the gate capacitance of the next stage, wiring capacitance) driven by the buffer and the wiring resistance R. The chip size increases with an increase in the memory capacity of the semiconductor device and the wiring length of a signal line is made longer, and therefore, the wiring delay time tends to become longer. When the size of the memory cell is reduced as the integration density of the semiconductor device is increased, the wiring width of the signal line extending over the memory cell must be reduced accordingly, and in this case, the distance between the adjacent wirings becomes short. Under this condition, the wiring delay time is increased. Further, as the time of access to the memory is made short, the rate of the wiring delay time determining the total access time becomes larger than in the conventional case. Thus, the wiring delay time cannot be neglected when an attempt is made to attain the high-speed operation. In order to suppress the wiring delay time, it is required to increase the wiring width and the space between the wirings.
Next, the conventional semiconductor device is explained by taking a static random access memory (SRAM) as an example to explain the problem of the wiring delay time. The SRAM is constructed by a memory cell array having memory cells arranged in a matrix form with a preset capacity, a row selection decoder and column selection decoder for selecting a desired memory cell, and a circuit for controlling input/output of data. As the element structure of the SRAM, a 6-transistor element such as a CMOS type element and E/D type element using depletion transistors as load elements is known in the prior art, however recently, resistance-load type elements having polysilicon resistors as high-resistance load elements are widely used. As shown in FIG. 1, since the high-resistance load type element (E/R type element) is a 4-transistor (Q1 to Q4) element and the resistance elements R1 and R2 of polysilicon can be laid over the upper layer of the MOS transistor, the cell occupied area can be reduced. A pair of transfer MOS transistors Q1, Q2 using the gate line as the gate input line are connected to respective storage nodes and read/write data transfer is effected between the memory cell and the data line via the transfer MOS transistors. The word line is connected to the output line of the row selection decoder and is formed by patterning a polysilicon layer which is the same as a polysilicon layer forming the gate electrode in the same step of forming the gate electrode, and the potential thereof is set at the "1" level to turn ON the transfer MOS transistors only when the memory cell 120 is selected.
A pair of data lines 106 are previously set at the same voltage level before the memory cell 120 is selected, so that data of a memory cell selected by the present address input can be protected and prevented from being erroneously written into a memory cell which will be selected by a next address input. In the case of write-in cycle, data transferred to the pair of data lines 106 according to data of the accessed memory cell 120 is written into the memory cell 120 via the transfer MOS transistors Q1, Q2 of the memory cell 120. The SRAM is so constructed as to select a desired memory cell from the memory cell array by driving the row decoder and column decoder and is variously designed to attain the high integration density, high-speed operation and low power consumption. In the SRAM, a stationary current flows from the data line load MOS transistor into all of the memory cells which are connected to a single word line via the transfer MOS transistors and driving MOS transistors at the time of readout or write-in for the memory cell. In order to reduce the stationary current at the time of operation, there is an approach in which the memory cell array is divided into a plurality of memory cell blocks by use of an address signal to reduce the number of memory cells connected to each of the word lines. For example, as shown in FIG. 2, the word line can be divided into small sections and the number of memory cells connected to each divided word line can be reduced by dividing the memory cells 120 into eight blocks (1) to (8) in the column direction and effecting the row selection for each block unit. FIG. 2 shows a row selection decoder 108, an assembly of a plurality of blocks of the memory cell array constructed by memory cells 120 selected by the row selection decoder, and a memory cell area 130.
The positional relation of the wirings of the SRAM on the semiconductor substrate is explained with reference to FIGS. 3 and 4. FIG. 3 is a plan view showing part of wirings on the semiconductor substrate and FIG. 4 is a cross sectional view taken along the line IV--IV of FIG. 3. The wirings used as signal lines, for example, are formed to extend over the memory cell area formed on the semiconductor substrate 110. Gate electrodes (not shown) of transistors constituting memory cells and second row selection lines 104 and memory cell ground potential line 171 which are formed of polysilicon are formed on an insulation film 111 on the semiconductor substrate formed of silicon, for example. The polysilicon wirings are covered with an insulation film 112 formed of silicon oxide, for example, and the insulation film 112 is made flat. Data lines 106 formed of wirings of a first metal wiring layers of A1, for example, for transferring data are formed on the insulation film. An insulation film 113 formed of silicon oxide, for example, is formed to cover the data lines 106 and is made flat. Wirings of a second metal wiring layers of Al, for example, are formed on the flattened surface of the insulation film 113 to intersect the data lines 106 at substantially right angles. The wirings of the second metal wiring layer are laid above memory cells 120 and are used as first row selection lines 101 of the memory cell array, shunt lines 103 of the second row selection lines 104 selected by the first row selection lines 101 and column selection lines 102, and shunt lines 107 for lowering the resistance of the memory cell ground potential lines 171.
The first row selection lines 101 are disposed adjacent to the respective shunt lines 103 of the second row selection lines 104. Further, the wirings 106 of the first metal wiring layers are electrically isolated from the wirings 101,103 and 107 of the second metal wiring layers by means of the insulation film 113. All of the wirings of the first and second metal wiring layers are disposed in one memory cell area 130 constructed by a memory cell and wirings, and as the memory size is reduced, the width of and the space between the wirings of the first and second metal wiring layers are reduced. As a result, the wiring resistance and the wiring capacitance are increased to further increase the wiring delay time. Particularly, the delay time becomes significant in the first row selection line 101 whose wiring length is large and which is formed of the wiring of the second metal wiring layer and disposed over the entire length of the memory cell array in the row direction thereof. Since the shunt lines 103 of the second row selection lines are divided for each column, the wiring length thereof is small and the delay time therein is not so long. Although not shown in the drawing, the second row selection line 104 is electrically connected to the shunt line 103 and the memory cell ground potential line 171 is electrically connected to the shunt line 107.
As the integration density of the semiconductor device is enhanced, the wiring width Lc of the first row selection line 101 and the wiring width Lb of the shunt line 103 of the second row selection line are reduced to increase the resistances thereof as shown in FIG. 4, for example, and the wiring interval Ls between the wirings 101 and 103 of the second metal wiring layer, that is, the space between the first row selection line 101 and the shunt line 103 is also reduced, and as a result, the capacitance CM between the wirings increases to make the wiring delay time of the semiconductor device long. Further, since the selection/non-selection mode of the first row selection line 101 and the shunt line 103 of the second row selection line 104 is set as shown in FIG. 5, the shunt line of the second row selection line is selected by use of the first row selection line 101 and the column selection line 102 when a NOR circuit 105 is used as the intermediate buffer. For this reason, signals in the first row selection line 101 and the second row selection line 104 in the cell selection state of the memory cell are set in the inverted relation. Therefore, the capacitance between the adjacent wirings is increased and the Miller effect becomes significant. As a result, the wiring delay time of the first row selection line 101 becomes long.
It is possible to reduce the wiring length of the first row selection line 101 of the second metal wiring layer by changing the memory cell array structure and increasing the number of memory cells connected to the data lines 106 of the first metal wiring layer, but the time delay effect in the data lines contained in the first metal wiring layer is larger and the substantially improved effect of reduction in the access time cannot be attained. Thus, as the integration density of the semiconductor device is more enhanced and the cell size is more reduced, it becomes more difficult to suppress an increase in the delay time of the wiring passing the memory cell area.